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preliminary uniclock cy22u1 single output, low power programmable clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-50320 rev. *c revised august 10, 2009 features small footprint, 8-pin qfn 1.7 x 1.7 x 0.6 mm 3 package low power and low jitter operation multiple operating voltages: ? cy22u1s: 2.5v, 3.0v, or 3.3v ? cy22u1l: 1.8v programmable single output clock generator frequency range: ? 1 to 200 mhz crystal or external reference clock input frequency range: ? fundamental tuned crystal: 8 to 48 mhz ? external reference clock: 1 to 166 mhz programmable capacitor tuning array programmable pd# or oe control pin programmable asynchronous or synchronous oe and pd# modes benefits services digital televisions and displays, set top boxes, multifunction printers, and a va riety of consumer electronics applications. saves pcb space due to small form factor. enables quick turnaround and flexibility and adaptability to design changes through programmability. enables synthesis of highly accurate and stable output clock frequencies with zero or low ppm error. enables fine tuning of output clock frequency by adjusting the crystal load c load using programmable internal capacitors. lowers clock solution cost by pairing a high frequency pll programmability with a low cost, low frequency crystal. enables low power during the power down or output disable function. provides flexibility for system ap plications through selectable asynchronous or synchronous output enable and disable. logic block diagram [+] feedback [+] feedback
preliminary uniclock cy22u1 document number: 001-50320 rev. *c page 2 of 11 pinouts figure 1. pin diagram - cy22u1 8-pin 1.7 x 1.7 mm 2 qfn functional description the uniclock cy22u1 is a programmable, high accuracy, pll-based clock generator device designed to replace crystals and crystal oscillators and save on cost and board space, while increasing reliability. the low jitter and accurate outputs makes this device suitable for use in digital televisions and displays, set top boxes, multifunction printe rs, and a variety of consumer electronics applications. the device has several programmable options listed in the section programmable features on page 4. the entire configuration is one time programmable. configurable pll the device uses a programmable pll to generate output frequencies from 1 to 200 mhz. the high resolution of the pll and flexible output dividers provide this flexibility. input referenc e clock option there is an option of a crystal or clock signal for the input reference clock. the frequency range for crystal (xin) is 8 mhz to 48 mhz, while the range for an external reference clock (clkin) is 1 mhz to 166 mhz. a pll bypass mode enables this device to be used as a crystal oscillator. multiple vdd power supply option the device has programmable power supply options. the operating supply voltages are 2.5v, 3.0v, or 3.3v for cy22u1s and 1.8v for cy22u1l. cy22u1 6 5 8 7 1 2 3 4 xout xin/clkin pd#/oe gnd nc clkout nc vdd table 1. pin definitions - cy22u1 8-pin 1.7 x 1.7 mm 2 qfn pin number name io description 1 xout output crystal output. float for external clock input. 2 xin/clkin input crystal or external clock input. 3 pd#/oe input multifunction pin. active low power do wn or active high output enable pin. has weak internal pull up. 4 gnd power power supply ground. 5 nc ? no connect. pin has no internal connection. 6 clkout output programmable clock output. output voltage depends on vdd. has weak internal pull down. 7 nc ? no connect. pin has no internal connection. 8 vdd power programmable power supply: cy22u1s: 2.5v, 3.0v, 3.3v (standard voltage) cy22u1l: 1.8v (low voltage) [+] feedback [+] feedback
preliminary uniclock cy22u1 document number: 001-50320 rev. *c page 3 of 11 power management feature the uniclock cy22u1 offers pd# (active low) and oe (active high) functions. when the power down mode is selected (pd# =0), the oscillator and pll are placed in a low supply current standby mode and the output is tr istated and weakly pulled low. the oscillator and pll circuits must relock when the part exits the power down mode. if the output is disabled (oe=0), the output is tristated and weakly pulled low. in this mode, the oscillator and pll circuits continue to operate, which enables a rapid return to normal operation when the output is enabled. i n addition, the pd# or oe mode can be programmed to occur asynchronously or synchronously with respect to the output signal. when the asynchronous setting is used, entering power down or disabling the output occurs immediately (enabling logic delays), regardless of the position in the clock cycle. similarly, exiting power down or enabling the output occurs immediately with no guarantee of full output clock pulses. however, when the synchronous setting is used, the part waits for a falling edge at the output before entering power down or disabling the output. this prevents output glitch es. the first output pulse is guaranteed to be a full clock pulse when enabling outputs with a synchronous oe pin. the first output pulse is not guaranteed to be a full clock when exiting power down in synchronous or asynchronous mode. output frequency tuning the uniclock cy22u1 contains an on-chip oscillator with a built in programmable capacitor array for fine tuning of the output frequency. the capacitive load seen by the crystal is adjusted by programming the memory bits. th is feature can compensate for crystal variations or provide a more accurate synthesized frequency. figure 2 shows the crystal oscillator tuning circuit block diagram. crystal oscillator tuning circuit figure 2. crystal oscillator tuning block diagram table 2. crystal oscillator tuning capacitor values cap value [1] unit c 7 5.000 pf c 6 2.500 pf c 5 1.250 pf c 4 0.625 pf c 3 0.313 pf c 2 0.156 pf c 1 0.078 pf c 0 0.039 pf c 7 x7 -r r f c 6 x6 c 5 x5 c 4 x4 c 3 x3 c 2 x2 c 1 x1 c xout c pxout c 7 x7 c 6 x6 c 5 x5 c 4 x4 c 3 x3 c 2 x2 c 1 x1 c xin c pxin f xin, esr, c 0 c 0 x0 c 0 x0 note 1. the capacitor values are nominal. [+] feedback [+] feedback
preliminary uniclock cy22u1 document number: 001-50320 rev. *c page 4 of 11 programmable features the following list of features can be custom configured: pll frequency and output divider value oscillator tuning (crystal load) capacitance value direct oscillator output (pll bypass) high or low power supply voltage operation power management mode (oe or pd#) power management timing (synchronous or asynchronous) programming support the device is available in factory and field programmable versions. the cyclockmaker programming kit along with cyclockdesigner configuration software is used to field program the device. for specific programming needs, contact your local cypress field application engineer (fae) or sales representative. absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. table 3. absolute maximum ratings parameter [2] description condition min max unit v dd supply voltage, 2.5v/3.0v/3.3v range ?0.5 4.4 v supply voltage, 1.8v range ?0.5 2.8 v v in input voltage relative to v ss ?0.5 v dd +0.5 v t s temperature, storage n on functional ?55 +125 c t j temperature, junction non functional ?40 +125 c esd hbm esd protection (human body mode l) jedec eia/jesd22-a114-e 2000 ? volts d ret data retention at t j = 125 c10 ? yr. pr cycle maximum programming cycle 1 ul-94 flammability rating v-0 at 1/8 in. msl moisture sensitivity level 3 recommended operating conditions parameter [2] description min typ max unit v dd supply voltage, 1.8v oper ating range for cy22u1l 1.6 ? 2.0 v supply voltage, 2.5v oper ating range for cy22u1s 2.2 ? 2.8 v supply voltage, 3.0v oper ating range for cy22u1s 2.7 ? 3.3 v supply voltage, 3.3v oper ating range for cy22u1s 3.0 ? 3.6 v t ac commercial ambient temperature 0?70c t ai industrial ambient temperature -40 ? 85 c t pu power up time for v dd to reach minimum specified voltage (power ramp must be monotonic) 0.05 ? 500 ms t pd minimum pulse width of pd#/oe input 100 ? ? ns c out output load capacitance ? ? 15 pf note 2. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. thes e are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute maximum rated conditions for extended periods may affect dev ice reliability or cause permanent device damage. [+] feedback [+] feedback
preliminary uniclock cy22u1 document number: 001-50320 rev. *c page 5 of 11 note 3. parameters are guaranteed by design and char acterization. not 100% tested in production. 4. v ih2 absolute maximum value is 2.1v. for v dd = 1.6v to 1.8v, the maximum v ih2 is v dd + 0.3v. dc electrical specifications parameter [3] description test conditions min typ max unit v il1 input low voltage of pd#/oe ? ? 0.2*v dd v v ih1 input high voltage of pd#/oe 0.8*v dd ?? v v il2 input low voltage of refin cy22u1s -0.2 ? 0.4 v cy22u1l -0.2 ? 0.4 v v ih2 input high voltage of refin cy22u1s 1.2 ? 2.1 v cy22u1l 1.2 ? v dd +0.3 [4] v v ol1 output low voltage i ol = 8 ma, v dd = 3.0/3.3v ? ? 0.4 v v oh1 output high voltage i oh = 8 ma, v dd = 3.0/3.3v v dd ? 0.4 ? ? v v ol2 output low voltage i ol = 4 ma, v dd = 1.8/2.5v ? ? 0.1*v dd v v oh2 output high voltage i oh = 4 ma, v dd = 1.8/2.5v 0.9*v dd ?? v i il input low current input = v ss ?<110 a i ih input high current input = v dd ?<110 a i ozl output leakage current output = v ss , tj = 85c ? <1 5 a i ozh output leakage current output = v dd ??50 a i dd power supply current for cy22u1l f out = 50 mhz, 15 pf load ? ? 7.5 ma f out = 200mhz, 15 pf load ? ? 15 ma power supply current for cy22u1s f out = 50 mhz, 15 pf load ? ? 10 ma f out = 200 mhz, 15 pf load ? ? 25 ma i pd power down current tj = 85c ? 25 50 a r up input pull up resistors pd#/oe = low pd#/oe = high 1 100 ? ? 6 250 m k r dn output pull down resistors 500 ? 1500 k c in input capacitance of pd#/oe pin ? ? 7 pf [+] feedback [+] feedback
preliminary uniclock cy22u1 document number: 001-50320 rev. *c page 6 of 11 notes 5. %t out is the percentage of the output clock period. 6. parameters are guaranteed by design and char acterization. not 100% tested in production. ac electrical specifications parameter [6] description test conditions min typ max unit f in (crystal) crystal frequency range (xin) 8 ? 48 mhz f in (clock) clock frequency range (refin) 1 ? 166 mhz f clk output frequency 1 ? 200 mhz t r output rise time measured from 20% to 80% v dd, c out = 15 pf ? ? 1.5 ns t f output fall time measured from 80% to 20% v dd, c out = 15 pf ? ? 1.5 ns dc output clock duty cycle using pll as a source 45 50 55 % t ccj cycle-to-cycle jitter of clkout using pll f out > 100 mhz 100 mhz > f out > 50 mhz f out < 50 mhz ? ? ? 75 150 ? 125 200 1 ps ps %t out [5] t p period jitter of clkout using pll f out > 100 mhz 100 mhz > f out > 50 mhz f out < 50 mhz ? ? ? 75 150 ? 125 200 1 ps ps %t out [5] t po,clk power on time for output clock ? ? 5 ms t pu,clk power up time from power down for output clock ? ? 5 ms t pd,async time from falling edge of pd# to stopped outputs, asynchronous mode ? ? 100 ns t pd,sync time from falling edge of pd# to stopped outputs, synchronous mode ? ? 1.5t + 100 ns t od,async time from falling edge of oe to stopped outputs, asynchronous mode ? ? 100 ns t od,sync time from falling edge of oe to stopped outputs, synchronous mode ? ? 1.5t + 100 ns t oe,async time from rising edge of oe to running outputs, asynchronous mode ? ? 100 ns recommended crystal specif ications for smd package parameter description range 1 range 2 range 3 unit f min minimum frequency 8 14 28 mhz f max maximum frequency 14 28 48 mhz r 1 maximum motional resistance (esr) 135 50 30 c 0 nominal shunt capacitance 4 4 2 pf c l nominal load capacitance 18 14 12 pf d l maximum crystal drive level 300 300 300 w [+] feedback [+] feedback
preliminary uniclock cy22u1 document number: 001-50320 rev. *c page 7 of 11 switching waveforms figure 3. clkout rise and fall time figure 4. duty cycle timing (dc) figure 5. period jitter figure 6. cycle to cycle jitter figure 7. power on timing t r v d d 0v t f 80% 20% clkout clkout t 1a t 1b v dd /2 dc =t 1a /t 1b clkout +3 v dd 0v j p ?3 +1 v dd /2 clkout v dd 0v t 1 t 2 t 3 t 4 t 5 t 998 t 999 t 1000 t ccj =max(t 2 -t 1 ,t 3 -t 2 ,t 4 -t 3 ,?,t 1000 -t 999 ) clkout v dd t ramp v dd 0v t po,out v dd 0v clock startup clkout [+] feedback [+] feedback
preliminary uniclock cy22u1 document number: 001-50320 rev. *c page 8 of 11 figure 8. power down timing (synchronous and asynchronous modes) and power up timing figure 9. clkout enable (synchronous and asynchronous modes) and clkout disabletiming v dd internal clock weakly pulled low clock startup clkout (sync) (async) t pd,async weakly pulled low t pu,out 1/f v dd v dd 0v t pd,sync clock startup t pu,out 0v v dd clock startup 0v 0v pd# clkout v dd 0v oe t oe,sync internal clock weakly pulled low (sync) (async) t od,async weakly pulled low v dd 0v v dd 0v t od,sync v dd 0v t oe,async clkout clkout [+] feedback [+] feedback
preliminary uniclock cy22u1 document number: 001-50320 rev. *c page 9 of 11 m notes 7. x indicates a part marking placeholder to distinguish differen t configurations for the same customer, beginning alphabeticall y from ?a?. 8. yy indicates ?factory programmable? and are factory programmed co nfigurations. for more details, contact your local cypress f ae or cypress sales representative. ordering information part number [7, 8] type vdd(v) production flow pb-free cy22u1scalgxc-00 8-pin qfn, field programmable supply vo ltage: 2.5v, 3.0v or 3.3v commercial, 0c to 70c cy22u1scalgxc-00t 8-pin qfn, field programmable - tape and reel s upply voltage: 2.5v, 3.0v or 3.3v commercial, 0c to 70c cy22u1lcalgxc-00 8-pin qfn, field programmable supply voltage: 1.8v commercial, 0c to 70c cy22u1lcalgxc-00t 8-pin qfn, field programmable - tape an d reel supply voltage: 1.8v commercial, 0c to 70c cy22u1scalgxi-00 8-pin qfn, field programmable supply volt age: 2.5v, 3.0v or 3.3v industrial, -40c to +85c CY22U1SCALGXI-00T 8-pin qfn, field programmable - tape and reel supp ly voltage: 2.5v, 3.0v or 3.3v industrial, -40c to +85c cy22u1lcalgxi-00 8-pin qfn, field programmable supp ly voltage: 1.8v industrial, -40c to +85c cy22u1lcalgxi-00t 8-pin qfn, field pr ogrammable - tape and reel supply voltage: 1.8v industrial, -40c to +85c cy22u1scxlgxc-yy 8-pin qfn supply voltage: 2.5v, 3.0v or 3.3v commercial, 0c to 70c cy22u1scxlgxc-yyt 8-pin qfn - tape and reel supply voltage: 2.5v, 3.0v or 3.3v commercial, 0c to 70c cy22u1lcxlgxc-yy 8-pin qfn supply voltage: 1.8v commercial, 0c to 70c cy22u1lcxlgxc-yyt 8-pin qfn - tape and reel supply voltage: 1.8v commercial, 0c to 70c cy22u1scxlgxi-yy 8-pin qfn supply voltage: 2.5v, 3.0v or 3.3v industrial, -40c to +85c cy22u1scxlgxi-yyt 8-pin qfn - tape and reel supply voltage: 2.5v, 3.0v or 3.3v industrial, -40c to +85c cy22u1lcxlgxi-yy 8-pin qfn supply voltage: 1.8v industrial, -40c to +85c cy22u1lcxlgxi-yyt 8-pin qfn - tape and reel supply voltage: 1.8v industrial, -40c to +85c (mmm) = 7 th , 8 th and 9 th characters of marketing part number mm m nnn (nnn) = last 3 digits of assembly lot number pin 1 indicator figure 1. actual marking [+] feedback [+] feedback
preliminary uniclock cy22u1 document number: 001-50320 rev. *c page 10 of 11 package drawing and dimensions figure 10. cy22u1 8-pin 1.7 x 1.7 x 0.6 mm 3 qfn 001-49591 ** [+] feedback [+] feedback
document number: 001-50320 rev. *c revised august 10, 2009 page 11 of 11 mobl is a registered trademark, and more battery life is a trademark, of cypress semiconductor. all product and company names m entioned in this document are the trademarks of their respective holders. preliminary uniclock cy22u1 ? cypress semiconductor corporation, 2008-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com document title: uniclock cy22u1 single outp ut, low power programmable clock generator document number: 001-50320 rev ecn orig. of change submission date description of change ** 2612925 cxq/aesa 11/26/2008 new data sheet *a 2636981 cxq/pyrs 01/15/09 updated part numbers in ordering information removed section on progra mmable output drive strength changed input range min from 8 mhz to 1 mhz changed input range from 200mhz max to 166mhz max replaced cyberclocksonlin e and cy3672 programmer reference with cyclockmaker and cyclockdesigner reference updated vih/vil specs for refin added typical i pd of 25ua added period jitter spec added marking format information updated package drawing to spec 001-49591 *b 2673516 cxq/pyrs 03/13/09 changed from advanced to preliminary datasheet deleted ?1.8v? when referri ng to external reference fixed error in device name for v il2 and v ih2 updated v ih2 maximum for cy22m1l and added note 4 added idd values to dc electrical specifications table *c 2748211 tsai 08/10/09 posting to external web. [+] feedback [+] feedback

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